Logic circuits for performing addition operations find many uses in Integrated Circuits (ICs), such as the circuits used in computers. For example, adders may be used to calculate addresses. Many applications for adder circuits also require an increment to be applied to the sum of the addition, for example to reflect a carry-in signal from another stage or circuit. In one particular example, an adder/incrementer circuit may be used as part of the back-end of a multiplier, to add two shifted numbers and perform a conditional increment, based on whether or not there is a need to round-up the resultant sum.
FIG. 13 provides a logical diagram of such an addition and conditional incrementer operation, preferably using a prefix adder type of circuitry. The illustrated circuit comprises an adder 11 and an incrementer 13, both of which may be implemented as prefix addition circuits. Prefix adders are binary adder circuits that compute the carries for the bit positions based on prefix equations. Prefix adders are described, for example, in Knowles, A Family of Adders, Element 14, Bristol, UK. [Proceedings of the 14th IEEE Symposium on Computer Arithmetic, pp. 30–34, Adelaide, Australia, April 1999] The logic needed to implement the carry chain in such an adder may be viewed as a prefix graph, illustrating the logical interconnection of the layers of the chain.
The adder (Σ) 11 adds two n-bit binary numbers A and B to produce an n-bit result (Sum) and an overflow or carry out bit (Overflow in the drawing). For some applications, the sum is incremented by adding a binary value of 1. For an application where it is desired to increment the value of the resultant Sum based on a conditional input (CarryIn), the illustrated incrementer 13 adds the conditional binary input value (CarryIn) to the Sum from the adder 11. As a result, the incrementer 13 produces a new n-bit result (IncrementedSum) and a new overflow or carry out bit (CarryOut in the drawing).
In some applications, the overflow bit from the adder 11 may be discarded. However, for an application where there is a need to determine the basis for the final carry out bit (CarryOut) associated with the IncrementedSum, it is possible to examine the value of the Overflow signal from the adder 11.
The implementation illustrated in FIG. 13, however, is not efficient, because the path through the adder 11 and the incrementer 13 passes through two n-bit wide carry chains, which requires a substantial amount of logic circuitry and introduces considerable delay. One solution to simplify the logic and reduce delay is to merge the incrementer with the adder into a single logic block 15, as illustrated in FIG. 14. In such an implementation, the incrementer 19 shares the carry chain (not separately shown) of the adder 17, and as such, requires only one stage of logic delay for the carry functions. This logical diagram shows the general form of the adder/incrementer 15, without showing the details. The logic circuitry for implementing the combined adder/incrementer 15 may be similar to a late carry in adder, which is one of the embodiments disclosed in published UK Patent Application No. (GB) 2342193 (published Apr. 5, 2000).
As noted, it is useful in some applications of the adder and incrementer to know the cause of the final CarryOut, and if the circuit is built as separate addition and incrementing circuits (FIG. 13), there is no problem in discriminating between the carry produced by the two separate operations. However, in the faster combined circuit 15 (FIG. 14), there is one problem. In such a circuit, the new CarryOut bit is not a function solely of any carry generated by the incrementer function. Instead, the new CarryOut bit may is a function of both the addition and the incrementing operation. Hence, there is a need for a combined adder/incrementer circuit that will also provide a signal indicative of the cause of the final CarryOut. Preferably, such a circuit should provide a CarryOut bit that depends solely on whether or not a carry signal is generated by the incrementer function.